Picture data memory device with picture data input channels and picture data output channels

ABSTRACT

A picture data memory device which can be used universally comprises a central picture data memory for storing picture data of a plurality of picture data input channels, in which case the stored picture data can additionally be read out via a plurality of picture data output channels for different kinds of further processing. A memory controller is provided for coordinating the individual storage operations of the picture data input channels and the individual rend-out operations of the picture data output channels.

BACKGROUND OF THE INVENTION

The present invention relates to a picture data memory device which canbe used universally.

Picture memories are increasingly being used in video signal processingin order to be able to implement complex picture processing algorithms,such as e.g. 100 Hz conversion, motion vector estimation or MPEGprocessing (Moving Pictures Experts Group). For this purpose, it isconventional practice for separate picture memory modules with separatecontrollers and separate memory paths to be provided for the individualpicture processing algorithms. However, it is often the case thatpicture data of a multiplicity of mutually asynchronous picture datachannels are present simultaneously (for example inPicture-In-Picture(PIP) Applications), with the result that in thiscase, when using the conventional technology, a correspondingly highoutlay on hardware is required in order to be able to store and processthe picture data of all the picture data channels.

SUMMARY OF THE INVENTION

The present invention is therefore based on the object of providing apicture data memory device which can be used universally and whichenables the storage and read-out of picture data of different inputchannels or picture data sources.

This object is achieved by means of a picture data memory device,according to preferred and advantageous embodiments of the presentinvention.

The present invention relates to a picture data memory device having acentral picture data memory for storing data of a plurality of picturedata input channels connected to the picture data memory, the centralpicture data memory additionally being connected to a plurality ofpicture data output channels for reading out and outputting storedpicture data for different types of further processing of the picturedata read out. The central picture data memory is assigned a memorycontroller which coordinates the individual storage and read-outoperations, thereby enabling all the required storage operations, i.e.the writing of picture data of different input channels and the read-outof any desired picture data via different output channels. The highmemory bandwidth of memory modules that are available nowadays isutilized for this purpose. All the input and output channels may beasynchronous. This relates both to the synchronization signals assignedto each picture data channel and to the associated sampling clocksignals, with regard to their frequency and phase.

The configuration of the picture data memory device according to theinvention takes account of the fact that, both at the input and at theoutput, continuous picture data streams have to be written and/or read.

For this purpose, corresponding measures are proposed in the input andoutput channels of the picture data memory device.

The individual storage and read-out operations are preferably processedby the memory controller in accordance with a specific priority scheme.All the input and output channels can be connected to the centralpicture data memory via a common memory bus, picture data beingtransferred from the input channels to the central picture data memory,or from the central picture data memory to the output channels via thememory bus. The memory controller accesses the central picture datamemory for addressing and control purposes.

The central picture data memory used may be inexpensive standardmemories, such as e.g. SDRAMs or eDRAMs (embedded DRAMs). The picturedata memory device according to the invention represents anoutlay-optimized system for all the memories required in the system andcan easily be configured by adding or omitting individual input oroutput channels. Smaller memory units, such as e.g. line memories, caneasily be implemented by adding a further channel.

Each input or output channel is advantageously assigned control oractivation signals which enable the picture data memory device to beeasily addressed by corresponding peripheral processing blocks.

Since asynchronous input and output channels can advantageously besupported according to the invention, complex picture processingalgorithms, such as e.g. so-called universal scan rate conversion (SRC)with conversion from the “50 Hz interlaced” mode into the “60 Hzprogressive” mode, can be realized more easily. Moreover,synchronization of asynchronous picture sources or input channels ispossible in a very simple manner, this being required, for example, inparticular in the case of the simultaneous representation of a pluralityof moving picture (multi-PIP representation).

The invention is explained in more detail below using preferredembodiments with reference to the accompanying drawing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic block diagram of the basic construction of apicture data memory device according to the invention,

FIGS. 2A and 2B show the construction of an input channel and outputchannel, respectively, shown in FIG. 1 in accordance with a preferredexemplary embodiment of the present invention, and

FIG. 3 shows the construction of the memory controller shown in FIG. 1in accordance with a further preferred exemplary embodiment of thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

As is indicated in FIG. 1, the picture data memory device according tothe invention comprises a central picture data memory 1, which isaddressed by a corresponding memory controller 2. A plurality of inputchannels 3 and a plurality of output channels 4 are connected to thecentral picture data memory 1 preferably via a common memory bus 5, withthe result that picture data of different sources can be written to thepicture data memory 1 and picture data can be read out and output fromthe picture data memory 3 for different applications or types ofprocessing. All the input and output channels can be asynchronous withrespect to one another, i.e. the individual channels 3 and 4 can beassigned synchronization signals SYNCIN and/or SYNCOUT and clock signalsCLOCKI/CLOCKO that are asynchronous with regard to their frequencyand/or phase.

The central picture data memory 1 may comprise for example one or moreSDRAM memory modules. Equally, it may be constructed from so-calledembedded DRAM or eDRAM memory modules, this solution being particularlyadvantageous since, on the one hand, the storage capacity and, on theother hand, at the same time the memory bandwidth can easily be adaptedto the respective requirements, the storage capacity being adaptedthrough the number of memory modules used and the memory bandwidth beingadapted by variation of the width of the data bus 5.

In the configuration of the picture data memory device shown in FIG. 1,it must be taken into account that, both at the input and at the outputof the picture data memory device, continuous picture data streamsDATAIN/DATAOUT have to be written and/or read. In contrast to a computermemory, for example, a picture data stream, during real-time pictureprocessing, cannot arbitrarily be halted if a capacity bottleneck occursat a point in the system, since, during real-time picture processing,immediate representation of the processed pictures on a screen ormonitor must be possible. For this purpose, the memory bandwidth at theinputs and outputs must also be large enough that each input 3 andoutput 4 can be continuously served even in the case of a maximumpossible data transfer from and to the picture data memory 1.

As has already been mentioned, each input channel 3 is assigned apicture data stream DATAIN, a clock signal CLOCKI, a synchronizationsignal SYNCIN marking the picture and line start, and a write activationsignal WREN, which identifies picture data that are to be written in ina valid manner. Correspondingly, each output channel 4 is assigned apicture data stream DATAOUT, a clock signal CLOCKO, a synchronizationsignal SYNCOUT and a read activation signal RDEN, with which the desireddata can be requested by the downstream blocks. The writing and read-outof picture data are effected via the common memory or picture data bus5, the memory controller 2 accessing the central picture data memory 1in order to address and drive the latter. For addressing purposes, eachinput and output channel 3 and 4, respectively, is preferably assignedan arbitrary address range in the picture data memory 1 to and fromwhich picture data can be written and read, respectively. Thischannel-specific address range is traversed by an address generator ofthe memory controller 2 generally beginning with a start addresslinearly through to a maximum address. As is shown in FIG. 3, in themost general case a dedicated address generator 11 is allocated to eachchannel 3 or 4 for this purpose.

The sequence of the addresses generated by the individual addressgenerators 11 can be manipulated as desired by the definition ofadditional control signals and parameters of the memory controller 2,with the result that it is possible, for example, only to write to orread from a part of the memory area of the picture data memory 1, inorder e.g. to “stamp” a size-reduced picture into a main picture or toread out only part of the whole picture. This can be realized forexample by the variable parameters “position within a line”, “number ofpixels”, and “number of lines” being defined for the memory controller.During read-out, this process of skipping one or more lines oralternatively the repetition of one or more lines is necessary fordifferent picture processing algorithms. For this purpose, it ispossible to define a respective control signal which is to be applied tothe memory controller and causes the address at the start of the line tobe correspondingly advanced or repeated.

The synchronization signals SYNCIN or SYNCOUT respectively assigned toeach input and output channel are fed to the memory controller 2, or theindividual address generators 11, in order to set the associated addressgenerator 11 to a defined start address at the start of a written orread picture or of a picture line.

In addition to generation of the memory addresses and control signalsfor the central picture data memory 1, a further essential task of thememory controller 2 is to coordinate all memory accesses of the inputand output channels 3 and 4, respectively. This task is performed by thepriority controller 10 shown in FIG. 3, which collects all the writerequest signals WREQ of the input channels 3 and read request signalsRDREQ of the output channels 4 and enters them according to specificcriteria into a list or queue which specifies the order in which theywill be processed. This list is updated with each newly arriving requestsignal and each processed request. The priority scheme followed by thepriority controller 10 may be, for example, such that a channeloperating at a high clock frequency is allocated a high priority and achannel operating at a low clock frequency is allocated a low priority.

As soon as a request of an input or output channel appears at thetopmost position in the above-mentioned processing list, the prioritycontroller 10 generates an activation signal ACT and transmits it to thecorresponding channel in order to initiate the data transfer associatedwith the request to be processed. In this way, this channel is allocateda time slot for the data transfer. Furthermore, the address generator 11of this channel generates an address for access to the picture datamemory 1 and generates the required control signals for the memoryaccess. The activation signal ACT can simultaneously be used forincrementing to the address. After the end of a memory access, thepriority controller 10 of the memory controller 2 immediately initiatesthe next data transfer by generating the activation signal ACT for thechannel which is now in first place in the processing list.Consequently, all the memory accesses are strung together in anuninterrupted manner, and the available memory bandwidth is utilizedoptimally.

In order to utilize the data rate of the picture data memory 2 as wellas possible, preferably a plurality of successive addresses are writtenor read during, a access (so-called page mode). For this purpose, abuffer memory is required in each input channel 3 and output channel 4.The construction of an input channel 3 is illustrated in FIG. 2A, whilethe construction of an output channel 4 is illustrated in FIG. 2B.

As can be gathered from the illustration of FIG. 2A, each input channel3 contains an input buffer 6, to which the corresponding picture dataDATAIN are fed continuously. The incoming picture data are collected inthe input buffer 6 until there are enough picture data to be able tocarry out a memory transfer. Once this state of occupancy has beenreached, a corresponding buffer controller 7 generates a write requestWRREQ, which is entered into the processing list by the prioritycontroller 10 shown in FIG. 3, and processed. Conversely, a reset signalReset can be fed to the buffer controller at any time by the memorycontroller 2.

Each output channel 4 also contains a buffer memory 8 and a buffercontroller 9. The picture data associated with a read operation and readfrom the picture data memory 1 are buffer-stored in the output buffer 8and slowly read out in order to ensure a continuous output data streamDATAOUT. Once the output buffer 8 has been emptied to such an extentthat new picture data can again be received from the main memory 1, theassociated buffer controller 9 generates a corresponding read requestRDREQ and communicates it to the memory controller 2 or the prioritycontroller 10 contained therein.

The capacity of the buffer memories 6 and 8 must in each case be greaterthan that volume of data which is transferred during a data transfer,since generally neither a write request WRREQ nor a read request RDREQcan be fulfilled immediately. Therefore, each input channel 3 or inputbuffer 6 must be able to buffer-store the incoming picture data duringthis waiting time. Conversely, each output channel 4 or output buffer 8must also be able to provide picture data during this waiting time inorder to ensure an uninterrupted picture data stream toward the outside.

In addition to the tasks described above, the buffer memories 6 and 8also convert the word width, in order to adapt the word width of theinput channel 3 or of the output channel 4 to that of the memory bus 5.If the word width of the input channel 3 is 8 bits, for example, thenthat of the memory bus 5 is 64 bits, for example, eight samples arecombined to form a 64-bit word which, proceeding from the buffer memory6, is transferred to the central picture data memory 1 via the memorybus 5. The adaptation is performed correspondingly the other way roundin the output channel 4.

In the buffer memories 6 and 8, in each case two different clock systemsmeet. The central picture data memory 1 operates with the memory clocksignal CLOCKM. The input buffers 6 are therefore written to with thechannel-specific clock signal CLOCKI and read from with CLOCKM, whilethe output buffers 8 are written to with CLOCKM and read from withCLOCKO. Such buffers or buffer memories can be realized for example withregister chains or SRAM modules. The individual clock signals CLOCKI,CLOCKM and CLOCKO can have different frequencies and phase angles.

As has already been mentioned, the memory controller 2 defines the orderin which requests of the input and output channels are processed, inaccordance with predetermined priorities. On the other hand, the memorycontroller 2 must also take care to ensure that each channel 3 or 4 isserved within an individually defined period of time, in order that thepicture data flow is not interrupted in an impermissible manner. Thisperiod of time depends on the clock rate and on the size of the buffermemory 6 or 8 respectively assigned to each channel 3 or 4. Generally,the entire picture data memory device should be dimensioned in such away as to ensure that all the write or read requests are alwaysfulfilled in good time, in order that the desired pixel or picture datasequence is ensured on all channels 3 or 4. To that end, the data ratesof the all the channels must be added and brought into accord with theachievable data rate of the central picture data memory 1 taking accountof all the instances of addressing. The system can be optimized withregard to the desired criteria in particular through a suitable choiceof the parameters “clock frequency CLOCKM of the picture data memory 1”,“size of the buffer memories 6 and 8”, “number of successive memoryaccess, (page mode cycles)” and “width of the memory bus 5”.

1. A picture data memory device, having a central picture data memoryfor storing picture data of a plurality of picture data input channelsconnected to the picture data memory, the picture data memoryadditionally being connected to a plurality of picture data outputchannels for reading out and outputting stored picture data for furtherprocessing of the output picture data, and having memory control meansfor coordinating the individual storage operations of the picture datainput channels and the individual read-out operations of the picturedata output channels, wherein each picture data input channel and eachpicture data output channel are assigned a synchronization signal, theindividual synchronization signals being fed to the memory controlmeans, and wherein the memory control means carry out coordinationbetween the individual storage operations of the picture data inputchannels and the individual output operations of the picture data outputchannels taking account of the corresponding synchronization signals. 2.The picture data memory device as claimed in claim 1, wherein thecentral picture data memory is an SDRAM memory.
 3. The picture datamemory device as claimed in claim 1, wherein the central picture datamemory is an eDRAM memory.
 4. The picture data memory device as claimedin claim 1, wherein in the presence of request signals of the individualinput and/or output channels for storing and/or for reading outcorresponding picture data, the memory control means co-ordinate andprocess these requests in accordance with a specific priority scheme. 5.The picture data memory device as claimed in claim 4, wherein each inputchannel comprises an input channel buffer memory which, on the inputside, receives and buffer-stores the picture data of the correspondinginput channel and, on the output side, is connected to the picture datamemory, and wherein each input channel buffer memory is assigned inputchannel control means which generate a storage request signal for thememory control means if a specific volume of picture data is stored inthe corresponding input channel buffer memory.
 6. The picture datamemory device as claimed in claim 5, wherein each output channelcomprises an output channel buffer memory which, on the input side, isconnected to the picture data memory and buffer-stores the picture dataof the corresponding output channel which are received from the picturedata memory, and wherein each output channel buffer memory is assignedoutput channel control means which generate a read-out request signalfor the memory control means if the corresponding output channel butlermemory has a specific free storage capacity.
 7. The picture data memorydevice as claimed in claim 6, wherein the input channel control meansare configured in such a way that, in the presence of a correspondingactivation signal from the memory control means, they initiate thestorage, in the picture data memory, of a volume of picture data storedin the corresponding input channel buffer memory, and wherein the outputchannel control means are configured in such away that, in the presenceof a corresponding activation signal from, the memory control means,they initiate the read-out of a specific volume of picture data from thepicture data memory and the storage of this volume of picture data inthe corresponding output channel buffer memory.
 8. The picture datamemory device as claimed in claim 7, wherein the capacity of each inputchannel buffer memory and of each output channel buffer memory isgreater than the volume of picture data transferred per storage orread-out operation.
 9. The picture data memory device as claimed inclaim 6, wherein the input channel buffer memory and the output channelbuffer memory are in each case formed by a register chain or an SRAMmemory.
 10. The picture data memory device as claimed in claim 6,wherein the input channel buffer memory and the output channel buffermemory are connected to the picture data memory via a common bus. 11.The picture data memory device as claimed in claim 4, wherein the memorycontrol means comprise address generator means for generatingchannel-specific address signals, and wherein the memory control means,for each request that is currently to be processed in accordance withthe specific priority scheme, generates an activation signal for thecorresponding input or output channel for carrying out the correspondingstorage or read-out operation and instructs the address generator leansfor generating a corresponding address signal for the picture datamemory.
 12. The picture data memory device as claimed in claim 11,wherein the address generator means comprise a dedicated addressgenerator for each input and output channel, and wherein thesynchronization signal of the corresponding input or output channel isapplied to each address generator, each address generator being set to aspecific start address of the picture data memory synchronously with thesynchronization signal applied to said address generator.
 13. Thepicture data memory device as claimed in claim 11, wherein thegeneration of the address signals by the address generator means can bemanipulated with the aid of corresponding control signals and/or withthe aid of corresponding parameterization.
 14. The picture data memorydevice as claimed in claim 1, wherein each picture data input channeland each picture data output channel are assigned a specific addressrange in the central picture data memory.
 15. The picture data memorydevice as claimed in claim 1, wherein at least two of the input channelsare asynchronous with respect to one another.
 16. The picture datamemory device as claimed in claim 1, wherein at least two of the outputchannels are asynchronous with respect to one another.
 17. The picturedata memory device as claimed in claim 1, wherein at least two input andoutput channels are asynchronous with respect to one another.